Synchronization in SDH/SONET

The master-slave clocking hierarchy (PRC, SSU, SEC), pointers, and dealing with jitter/wander.

The Conductor's Baton: Why Timing is Everything in Digital Networks

Imagine a large orchestra where each musician plays to their own internal rhythm. The result would be chaos, not music. A modern telecommunications network is much like an orchestra, but instead of musicians, it has thousands of interconnected devices (multiplexers, switches, and regenerators). Instead of notes, they handle billions of bits of data per second. For this complex system to function, every single device must play in perfect time, guided by a shared, ultra-precise rhythm. This process of ensuring timing harmony across the entire network is called synchronization.

In earlier , devices had their own "nearly synchronous" clocks, leading to timing conflicts that required complex and inefficient fixes. SDH/SONET was revolutionary because it was designed from the ground up as a fully synchronous system, where ideally, every device follows the beat of the same metaphorical conductor's baton. However, ensuring this perfection in a real-world, continent-spanning network is a profound engineering challenge.

When Clocks Disagree: The Impact of Desynchronization

In any transmission system, the receiver needs to know the precise moment to sample the incoming signal to correctly identify a '1' or a '0'. This is governed by its local clock. If the receiver's clock and the transmitter's clock are not perfectly aligned, errors are inevitable.

Buffer Overflow and Underflow

To compensate for minor timing differences, receiving equipment uses small memory buffers. The incoming data is written to the buffer using the recovered timing of the sender's clock, and read from it using the receiver's local clock.

  • Overflow: If the sender's clock is faster than the receiver's clock, data arrives faster than it is read. Eventually, the buffer will overflow, and incoming bits will be lost.
  • Underflow: If the sender's clock is slower than the receiver's clock, data is read faster than it arrives. Eventually, the buffer will become empty (underflow), and the receiver will either read old data again or register an error.

The Result: Controlled Slips

When a buffer overflows or underflows, the network experiences a slip. A slip is a controlled data error where an entire frame of data (in PDH) or a block of bytes (in SDH) is either deleted (on overflow) or repeated (on underflow) to reset the buffer and prevent a catastrophic loss of synchronization. While controlled, slips are still data corruption and their impact varies dramatically depending on the service:

  • Uncompressed Voice (Telephony): A single slip results in an audible, but usually harmless, "click" or "pop" in the audio.
  • Fax/Modem Data: A slip causes a burst of errors, corrupting a portion of the transmission and almost always requiring the retransmission of that data block.
  • Compressed Video: A slip can be catastrophic. Due to inter-frame compression, a single corrupted byte can cause severe, visible distortion (blockiness, freezing) that persists for several seconds until the next full reference frame arrives.

International standards (like ITU-T G.821) define strict performance objectives, specifying the acceptable number of slips per day for different parts of a network, highlighting how critical timing stability is.

Jitter and Wander: The Enemies of Timing Stability

Slips are the result of long-term frequency offsets. However, there are also short-term timing variations known as phase fluctuations. These are unwanted deviations of signal transitions from their ideal positions in time. Depending on their speed, they are classified into two categories:

Jitter

refers to high-frequency variations in signal timing (conventionally above 10 Hz). It's like a rapid "tremor" or "vibration" of the signal's phase. It can be caused by electronic noise, non-ideal component behavior, and even the data pattern itself (pattern-dependent jitter).

Wander

refers to low-frequency, long-term drift in signal timing (below 10 Hz). It's like a slow "drifting" or "meandering" of the signal's phase. Its primary causes are temperature changes affecting oscillators and the minuscule, but cumulative, frequency differences between independent primary network clocks (e.g., at the border between two national networks).

The Master-Slave Solution: The SDH/SONET Clocking Hierarchy

To prevent slips and control jitter and wander, SDH/SONET employs a strict, centralized, master-slave hierarchical synchronization strategy. This ensures that every device in the network derives its timing from a single, ultra-stable source, preventing timing conflicts from arising.

Diagram hierarchii zegarowej SDH

Tier 1: The Primary Reference Clock (PRC)

At the very top of the hierarchy is the PRC, the "grandmaster" clock for an entire national or regional network.

  • Function: To provide an extremely stable and accurate timing reference signal (Stratum1Stratum\ 1 quality).
  • Technology: PRCs are typically based on atomic clocks, most commonly Cesium standards, or are locked to signals from the Global Positioning System (GPS), which itself uses on-board atomic clocks. In the US, the official time sources are the master clocks at the U.S. Naval Observatory (USNO) and the National Institute of Standards and Technology (NIST).
  • Requirements: Due to their extreme sensitivity, PRCs require highly controlled environments with stable temperature, humidity, and no vibrations.

Tier 2: The Synchronization Supply Unit (SSU) / Building Integrated Timing Supply (BITS)

SSUs (or BITS clocks in North American terminology) are high-quality slave clocks located in major network nodes (central offices).

  • Function: An SSU receives one or more timing reference signals from a PRC (or another SSU). It selects the best quality input, filters out any accumulated jitter, and distributes a regenerated, clean timing signal to all the equipment within that node.
  • Holdover Mode: A crucial feature is the SSU's ability to enter "holdover" mode. If it loses all its external timing references, its internal high-stability oscillator (e.g., Rubidium) can maintain a highly accurate clock signal for an extended period (hours or even days), preventing the node from losing synchronization.

Tier 3: The Synchronous Equipment Clock (SEC)

The SEC is the clock built into every piece of SDH/SONET equipment, such as an Add-Drop Multiplexer or a Cross-Connect.

  • Function: The SEC derives its timing from one of its incoming STM/OC data links or from a dedicated SSU/BITS output. It uses this recovered clock to time all of its internal operations and its outgoing transmissions. It is a slave to the timing it receives.

Communication and Control: The Synchronization Status Message (SSM)

With multiple potential timing sources available at each node, how does the equipment know which one to trust? The answer lies in the Synchronization Status Message (SSM).

The SSM is a small piece of data (4 bits) carried in a dedicated byte (S1 byte) within the Multiplex Section Overhead (MSOH) of every SDH/SONET frame. This message communicates the quality level (also called Stratum level) of the clock that timed the signal.

SSM Value (Binary)Clock Quality LevelMeaning
0001QL-PRC (Stratum 1)Traceable to Primary Reference Clock (Highest Quality)
0000QL-SSU-A (Stratum 2)Traceable to a high-quality SSU/BITS clock
1000QL-SSU-B (Stratum 3)Traceable to a standard SSU/BITS clock
1111QL-DNUDo Not Use for synchronization. (Signal quality is too low)

Each network element continuously monitors the SSM on all its inputs. It will automatically select the input with the highest quality clock (lowest stratum number) as its timing reference. If that reference fails, it will switch to the next-best available source. This simple but powerful mechanism prevents timing loops and ensures that the entire network remains robustly synchronized to the best available clock source.

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