The Core Problem: "Near-Synchronous" isn't Synchronous

The name "Plesiochronous" means "nearly synchronous." This points to the central challenge in PDH: how do you combine several digital streams (tributaries), each with its own highly accurate but slightly different clock, into a single, faster stream?

Imagine four E1 streams, each nominally 2.048 Mbit/s, arriving at an E2 multiplexer. One stream might actually be running at 2.04801 Mbit/s, while another runs at 2.04799 Mbit/s due to minute clock imperfections. If you tried to simply interleave their bits using a perfect clock, the buffer for the faster stream would eventually overflow, and the buffer for the slower stream would run empty. This would lead to bit slips and data corruption.

The Solution: Bit Stuffing (Justification)

PDH solves this timing mismatch with a clever technique called justification, also commonly known as bit stuffing. The principle is to make the higher-level stream's capacity slightly larger than what is theoretically needed and use the extra space to accommodate timing differences.

How Justification Works

1. Excess Capacity: The higher-level multiplexer (e.g., E2 at 8.448 Mbit/s) runs at a bit rate that is slightly higher than the sum of the nominal rates of its four E1 tributaries ($4 \times 2,048 = 8,192 \text{ Mbit/s}$). This creates extra bit slots in the output frame.
2. Justification Opportunity: Within the structure of the higher-level frame, there is a pre-defined bit position for each tributary called the "justification opportunity time slot" or "stuffable bit slot."
3. The Decision: For each tributary, the multiplexer monitors the state of its input buffer.
   • If the tributary is running slower than its allocated capacity, the buffer will start to empty. To prevent this, the multiplexer inserts a "stuffing" bit (a dummy bit with no information) into the justification opportunity slot.
   • If the tributary is running faster, its buffer will fill up. The multiplexer then uses the justification opportunity slot to transmit an actual data bit from the tributary.
4. Control Signal: To inform the receiver what to do, the multiplexer sends a signal using separate Justification Control Bits within the frame overhead. For reliability, this is often a 3-bit or 5-bit majority vote code (e.g., `111` means "stuffing bit present," `000` means "data bit present").

The Consequence: Justification Jitter

While justification solves the synchronization problem, it introduces its own artifact: justification jitter, also known as "waiting-time jitter."

At the demultiplexer, the stuffing bits are removed based on the control bits, and the original tributary data is read out into another elastic buffer. The read-out clock must be smooth and at the average frequency of the original tributary. However, the data arrives unevenly (sometimes there is a data bit in the justification slot, sometimes there is a gap). This uneven arrival of data causes the buffer's fill level to fluctuate, which translates into low-frequency phase variations (jitter and wander) on the reconstructed clock signal.

This jitter is a fundamental characteristic of PDH and must be filtered out by a Phase-Locked Loop (PLL) in the receiving equipment to restore a clean, stable clock for the tributary stream before it is sent further.