Bit Justification Mechanism

Plesiochronous timing and independent clocks

The term "plesiochronous" means "nearly synchronous." ITU-T G.810 describes each tributary as having its own timing source. The nominal frequencies are equal, but small frequency offsets remain, so the multiplexer must combine the tributaries into one higher-rate stream.

Consider four E1 streams, each with a nominal rate of 2.048 Mbit/s, arriving at an E2 multiplexer. One can run at 2.04801 Mbit/s while another runs at 2.04799 Mbit/s because of clock differences. Interleaving with a fixed output clock would gradually fill the faster tributary's buffer and empty the slower tributary's buffer. Without rate adaptation, the buffer limits would cause slips and loss of data.

Positive justification

PDH compensates for frequency differences with justification, also called pulse stuffing. In positive justification, the higher-level stream has more capacity than the sum of the tributaries' nominal rates. Designated positions absorb the difference between the incoming clocks and the output clock.

How positive justification works

1. Excess capacity: An E2 multiplexer runs at 8.448 Mbit/s, above the nominal sum of four E1 tributaries ($4 \times 2.048 = 8.192 \text{ Mbit/s}$). The 0.256 Mbit/s difference provides positions available for justification and frame overhead.
2. Justification position: The higher-level frame provides one J position for each tributary. The position carries either a data bit or a stuffing bit.
3. The decision: For each tributary, the multiplexer monitors the fill level of its input buffer.
   • If the tributary is slower than its allocated capacity, its buffer starts to empty. The multiplexer places a stuffing bit, which carries no tributary information, in the J position.
   • If the tributary is faster, its buffer fills up. The multiplexer uses the J position to transmit an actual data bit from the tributary.
4. Control signal: The multiplexer tells the receiver how to interpret the J position with separate justification-control bits in the frame overhead. G.751 recommends majority voting. At E3, three C bits encode each tributary decision; at E4, five C bits do so. The code 111 or 11111 signals positive justification, while 000 or 00000 signals no justification.

The mechanism described here is positive justification. ITU-T G.745 also specifies PDH variants with positive, zero, or negative justification, in which the justification position has a different function. The C-bit decisions belong to the frame overhead and do not change the frame length.

Justification jitter and clock recovery

Justification compensates for frequency differences but introduces its own phase variation: justification jitter, also called waiting-time jitter. ITU-T O.171 uses this name for the low-frequency phase variation produced by pulse-justification demultiplexers.

At the demultiplexer, the control bits determine whether each J position is retained or discarded, and tributary data is written to an elastic buffer. The read-out clock is smoothed and runs at the tributary's average frequency. Data still arrives unevenly because a J position sometimes contains a data bit and sometimes a stuffing bit. ITU-T G.810 classifies phase variation at frequencies of 10 Hz and above as jitter and below 10 Hz as wander, so the stuffing pattern can contribute to both components.

The receiving equipment smooths this variation with clock-recovery circuitry, often a Phase-Locked Loop (PLL). The loop restores a stable tributary clock before further transmission; G.751 specifies interface limits rather than one required circuit topology.

For the 139.264 Mbit/s equipment interface, G.751 limits E3 tributary-output jitter to 0.3 UI peak-to-peak up to 800 kHz and to 0.05 UI in the 10 kHz to 800 kHz measurement band, with 99.9% probability over 10 seconds. The composite E4 output limit is 0.05 UI peak-to-peak from 200 Hz to 3.5 MHz. ITU-T G.823 specifies a minimum E4 input tolerance of 0.075 UI from 10 kHz to 3.5 MHz, where 1 UI equals 7.18 ns.