The Dual Challenge of a Digital Stream

An E1 stream is essentially a continuous river of 2,048,000 bits flowing every second. For a receiver to make sense of this, it must solve two fundamental problems:

1. The Alignment Problem: How does the receiver find the exact start of each 256-bit frame and each 16-frame multiframe within this endless stream? Without clear markers, the data is meaningless.
2. The Integrity Problem: How can the receiver verify that the received data has not been corrupted by noise or interference during transmission?

The E1 standard elegantly solves both problems by using the overhead bits within the multiframe structure, primarily within Time Slot 0 (TS0).

Finding the Way: Frame and Multiframe Alignment

The E1 multiframe uses specific, unique bit patterns as "signposts" that allow the receiver to synchronize itself to the incoming data structure.

• Frame Alignment Word (FAW) in TS0: The receiver first searches for the Frame Alignment Word, the 7-bit pattern `0011011`. This pattern is transmitted in Time Slot 0 of every even-numbered frame (Frames 0, 2, 4,...). Once the receiver repeatedly finds this pattern at 256-bit intervals, it knows it has achieved frame synchronization.
• Multiframe Alignment Word (MFAW) in TS16: After achieving frame sync, the receiver then looks for the Multiframe Alignment Word, the 4-bit pattern `0000`. This pattern is transmitted only in the first 4 bits of TS16 of Frame 0. Detecting the MFAW signals the start of a new 16-frame cycle, which is essential for correctly decoding the Channel Associated Signaling (CAS) information that follows in Frames 1-15.

Ensuring Integrity: The CRC-4 Mechanism

To monitor the quality of the transmission link, the E1 standard includes a built-in error-checking mechanism called CRC-4. This mechanism does not correct errors, but it effectively reports them, allowing network operators to monitor link performance.

How CRC-4 Works

1. Block Calculation: The transmitter groups the frames of one multiframe into a block (specifically a sub-multiframe or SMF). It takes all 2048 bits of this block and performs a polynomial division calculation, which results in a 4-bit remainder. This 4-bit value is the CRC checksum.
2. Transmission: These 4 checksum bits are then transmitted in the TS0 of odd-numbered frames within the next multiframe. Each odd-numbered frame carries one bit of the 4-bit CRC value.
3. Verification: The receiver performs the exact same polynomial division on the data it received in the corresponding block. It then compares its calculated 4-bit checksum with the 4-bit checksum it received from the transmitter. If the values do not match, the receiver knows that at least one bit error occurred in that block of 2048 bits and can report a CRC error.

This continuous error-checking provides a powerful tool for link quality monitoring, which was a significant improvement over older PDH systems that lacked such integrated capabilities.