CRC-4 and Alignment

E1 Frame and Multiframe Alignment

An E1 signal carries 2,048,000 bits per second in 256-bit frames. A receiver must establish frame boundaries and interpret the 16-frame CRC-4 and CAS multiframe structures. It also needs a check that identifies transmission errors.

1. Frame and multiframe alignment: The receiver finds the start of each 256-bit frame and the relevant 16-frame multiframe by locating defined alignment patterns.
2. Error detection: The receiver checks whether noise or interference changed the transmitted data.

The E1 frame structure places frame alignment in Time Slot 0 (TS0); when CRC-4 is configured, its overhead also uses bit 1 of TS0. Channel Associated Signaling (CAS) uses a separate 16-frame structure in TS16.

E1 Frame and Multiframe Alignment Patterns

E1 frame structures use defined bit patterns that let the receiver recover the frame and multiframe position.

• Frame Alignment Signal (FAS) in TS0: The receiver searches for the 7-bit pattern 0011011 in bits 2-8 of TS0 in every even-numbered frame (Frames 0, 2, 4,...). Repeated detection at 256-bit intervals establishes frame synchronization. When CRC-4 is used, bit 1 of these frames carries a CRC-4 check bit.
• Multiframe Alignment Signal (MFAS) in TS16: For CAS, the eight bits of TS16 in Frame 0 have the form 0000xyxx. The first 4 bits, 0000, mark the start of the 16-frame CAS cycle. The x bits are spare and set to 1 when unused. The y bit carries the remote alarm indication, with 0 for normal operation and 1 for an alarm. This TS16 structure is separate from CRC-4 multiframe alignment. In CRC-4, bit 1 of TS0 carries the six-bit MFAS sequence 001011 across non-FAS frames 1, 3, 5, 7, 9 and 11. Bit 1 of frames 13 and 15 carries the CRC-4 error indication bits E.

CRC-4 Error Detection

To monitor the quality of a transmission link, an E1 configuration can use an error-checking mechanism called CRC-4. CRC-4 detects errors and supports link-performance monitoring. A separate function must handle corrupted data.

The CRC-4 Procedure

1. Block calculation: A CRC-4 block is one 8-frame sub-multiframe (SMF) containing 2,048 bits. The transmitter replaces the four CRC positions with zeroes, multiplies the SMF polynomial by x⁴, and divides modulo 2 by the generator polynomial x⁴ + x + 1. The remainder has four bits, with C1 as the most significant bit and C4 as the least significant bit.
2. Transmission: In SMF I, bits C1-C4 occupy bit 1 of TS0 in FAS frames 0, 2, 4, and 6. In SMF II, they occupy frames 8, 10, 12, and 14, respectively. Each four-bit set is the remainder calculated for the preceding SMF. Bit 1 of TS0 carries the six-bit CRC-4 multiframe alignment pattern 001011 across non-FAS frames 1, 3, 5, 7, 9 and 11. Bit 1 of frames 13 and 15 carries the E bits that report errors detected in received SMFs.
3. Verification: The receiver extracts the received CRC bits, replaces their positions with zeroes, and repeats the multiplication and division for the corresponding 2,048-bit SMF. It compares the calculated remainder with the CRC bits received in the following SMF. A mismatch indicates at least one detected error in the checked block.

Equipment can count CRC mismatches for each SMF and use them to monitor the quality of the E1 path.