Successive Approximation ADC

A widely used method balancing speed and resolution via iterative comparisons.

The "Goldilocks" of Converters

The Successive Approximation ADC, also known as a weighted compensation converter, is one of the most popular and versatile types of analog-to-digital converters. It strikes an excellent balance between speed, resolution, and cost, making it a "just right" solution for countless applications.

Its core principle is the method of sequential comparisons, which works like a very efficient guessing game. Instead of comparing the input voltage to hundreds of references at once like a Flash ADC, it systematically narrows down the possibilities one bit at a time, performing a binary search to find the correct digital representation.

Architecture and Key Components

The SAR ADC architecture is elegant and efficient, built around four critical components that work in a feedback loop.

Block diagram of a Successive Approximation ADC

Successive Approximation Register (SAR): This is the digital "brain" of the converter. It's a logic circuit that generates the binary code to be tested at each step of the conversion. It intelligently sets, keeps, or resets bits based on the comparator's feedback.
Digital-to-Analog Converter (DAC): The DAC takes the binary code "guess" from the SAR and converts it back into an analog voltage ( $U_{DAC}$ ). This generated voltage is what gets compared to the actual input voltage.
: This component compares the unknown input voltage ( $U_{we}$ ) with the test voltage ( $U_{DAC}$ ) from the DAC. It outputs a single bit ('1' or '0') telling the SAR whether its guess was too high or too low.
Clock: A clock signal synchronizes the entire operation, ensuring that each of the $N$ comparison steps for an $N$ -bit conversion occurs in a precise, sequential order.

The Conversion Process: A Step-by-Step Example

The best way to understand the successive approximation method is to walk through an example. Let's imagine a 4-bit ADC with a reference voltage of $U_{REF} = 16\text{V}$ , trying to convert an input voltage of $U_{we} = 11.5\text{V}$ . The conversion will take 4 clock cycles.

Cycle 1 (MSB - Most Significant Bit): The SAR sets the MSB to 1. The binary guess is '1000'. The DAC converts this to $1/2 \cdot U_{REF} = 8\text{V}$ . The comparator checks: Is $11.5\text{V} > 8\text{V}$ ? Yes. Therefore, the SAR keeps the MSB as '1'. Current result: '1xxx'.
Cycle 2 (Next Bit): The SAR sets the next bit to 1. The binary guess is '1100'. The DAC converts this to $(1/2 + 1/4) \cdot U_{REF} = 12\text{V}$ . The comparator checks: Is $11.5\text{V} > 12\text{V}$ ? No. Therefore, the SAR resets this bit to '0'. Current result: '10xx'.
Cycle 3 (Next Bit): The SAR keeps the current state '10' and sets the next bit to 1. The guess is '1010'. The DAC converts this to $(1/2 + 0/4 + 1/8) \cdot U_{REF} = 10\text{V}$ . The comparator checks: Is $11.5\text{V} > 10\text{V}$ ? Yes. Therefore, the SAR keeps this bit as '1'. Current result: '101x'.
Cycle 4 (LSB - Least Significant Bit): The SAR keeps the current state '101' and sets the last bit to 1. The guess is '1011'. The DAC converts this to $(1/2 + 0/4 + 1/8 + 1/16) \cdot U_{REF} = 11\text{V}$ . The comparator checks: Is $11.5\text{V} > 11\text{V}$ ? Yes. Therefore, the SAR keeps this bit as '1'. Final result: '1011'.

After $N$ cycles, the register holds the final digital value. For an N-bit converter, this entire process takes $N$ comparisons to complete.

Evaluation of the Method

Advantages

Good Speed: Much faster than integrating ADCs, as it only requires N clock cycles for an N-bit conversion.
High Resolution: Can achieve high resolutions (12, 16, or more bits) without the exponential increase in complexity seen in Flash converters.
Low Cost and Power: The architecture is relatively simple, consisting of only one comparator and one DAC, making it cost-effective and power-efficient.
Easy Implementation: It is a well-understood and common architecture in integrated circuits.

Disadvantages

Slower than Flash: The sequential nature of the conversion makes it inherently slower than the fully parallel Flash architecture.
Requires a Stable Input: The input voltage must remain constant during the entire N-cycle conversion process. A changing input can lead to an incorrect result. For this reason, SAR ADCs are almost always preceded by a circuit.