Successive Approximation ADC

Successive-approximation ADC

A successive-approximation ADC, usually called a SAR ADC, converts a sampled input by binary search. The architecture reuses one comparator and one DAC for the decisions, so its speed, resolution, power, and cost depend on the implementation and operating conditions.

Its core principle is the method of successive comparisons. Unlike a Flash ADC, which uses parallel comparators for many thresholds, a SAR ADC tests one binary weight at a time and narrows the code range until every bit has been decided.

Architecture and Key Components

A basic SAR ADC contains four main signal-path blocks and timing logic. The sample-and-hold keeps the input fixed while the DAC, comparator, and SAR determine the bits in sequence.

Successive Approximation Register (SAR):This logic circuit generates the trial code at each conversion step. It sets, retains, or clears a bit according to the comparator's decision.
Digital-to-Analog Converter (DAC): The DAC converts the SAR trial code into an analog voltage ( $U_{DAC}$ ). The comparator compares that voltage with the held input.
: This component compares the held input voltage ( $U_{in}$ ) with the test voltage ( $U_{DAC}$ ) from the DAC. It outputs one bit ('1' or '0') that tells the SAR whether to retain or clear the trial bit.
Clock: A clock signal sequences the comparison steps. An $N$ -bit conversion requires $N$ bit decisions in the ideal core algorithm.
: This circuit acquires the analog input and holds it during the bit decisions. Some SAR ADCs integrate this function into the input network or DAC.

The Conversion Process: A Step-by-Step Example

Consider a 4-bit ADC with a reference voltage of $U_{REF} = 16\text{ V}$ and a held input voltage of $U_{in} = 11.5\text{ V}$ . The ideal binary search makes 4 comparison decisions. Acquisition, DAC settling, and interface timing can add clock periods in a physical device.

Cycle 1 (MSB, Most Significant Bit): The SAR sets the MSB to 1. The trial code is '1000'. The DAC produces $1/2 \cdot U_{REF} = 8\text{ V}$ . The comparator checks $11.5\text{ V} > 8\text{ V}$ , so the SAR keepsthe MSB at 1. Current result: '1xxx'.
Cycle 2 (next bit): The SAR sets the next bit to 1. The trial code is '1100'. The DAC produces $(1/2 + 1/4) \cdot U_{REF} = 12\text{ V}$ . The comparator checks $11.5\text{ V} > 12\text{ V}$ , which is false, so the SAR clearsthis bit to 0. Current result: '10xx'.
Cycle 3 (next bit): The SAR retains '10' and sets the next bit to 1. The trial code is '1010'. The DAC produces $(1/2 + 0/4 + 1/8) \cdot U_{REF} = 10\text{ V}$ . The comparator checks $11.5\text{ V} > 10\text{ V}$ , so the SAR keepsthis bit at 1. Current result: '101x'.
Cycle 4 (LSB, Least Significant Bit): The SAR retains '101' and sets the last bit to 1. The trial code is '1011'. The DAC produces $(1/2 + 0/4 + 1/8 + 1/16) \cdot U_{REF} = 11\text{ V}$ . The comparator checks $11.5\text{ V} > 11\text{ V}$ , so the SAR keepsthis bit at 1. Final result: '1011'.

After $N$ bit decisions, the register holds the final digital code. An $N$ -bit converter therefore needs $N$ comparisons in the ideal algorithm; acquisition and other timing phases are implementation-dependent. The example input is exactly halfway between codes 11 and 12, so the shown strict comparison convention returns code 11; another tie rule could return code 12.

Evaluation of the Method

Advantages

Conversion time: The binary search requires one bit decision per bit, so the ideal core uses N comparisons. Throughput also depends on the conversion clock, acquisition, and settling time.
High resolution: Can achieve high resolutions (12, 16, or more bits) without the exponential increase in complexity seen in Flash converters.
Shared analog blocks: One comparator and one DAC are reused for all bit decisions. This can reduce circuit area and power compared with architectures that use many comparators, although the device design sets the actual values.
Easy implementation: It is a well-understood and common architecture in integrated circuits.

Disadvantages

Sequential decisions: For a comparable conversion clock, the bit-by-bit process requires more decision periods than a fully parallel Flash architecture.
Input acquisition: The voltage being converted must remain stable during the bit decisions. A changing input can produce an incorrect code. A SAR ADC therefore needs a circuit, either integrated or external.