Flash A/D Converters

Flash ADC: Overview

The Flash analog-to-digital converter, also known as a parallel ADC, converts an analog signal into a digital signal. Its defining characteristic is a short conversion time. It belongs to the family of direct conversion methods, in which the input voltage is compared with many reference levels in parallel.

Parallel comparator operation provides high speed and low latency. Flash ADCs are used in applications such as digital oscilloscopes, high-speed data acquisition systems, and software-defined radio when a high sampling rate is required.

Architecture and Components

The architecture of a Flash ADC is conceptually simple, but the number of comparators and ladder taps grows exponentially with resolution. For an $N$-bit converter, it consists of three main parts:

1. Resistor ladder: In the simplified arrangement, a chain of $L_R = 2^N$ equal resistors with value R is connected between the reference voltage ($U_{REF}$) and ground. It acts as a voltage divider and establishes $2^N-1$ reference thresholds for comparison.
2. Comparator bank: A bank of $L_K = 2^N - 1$ analog comparators. The unknown input voltage $U_{IN}$ is fed simultaneously to one input of every comparator. The other input of each comparator is connected to a different ladder tap, which establishes a separate reference threshold.
3. Decoder: The outputs of all $2^N - 1$ comparators are fed into a priority encoder. This logic circuit converts the comparator outputs, which form a "thermometer code" with a string of 1s followed by a string of 0s, into an $N$-bit binary number representing the quantized input value.

Operating parameters

Flash ADC operation is described by several basic parameters:

• Resolution ($\Delta U$): This is the smallest input-voltage change that an ideal converter can distinguish. For an input range from 0 to $U_{REF}$, it is determined by the reference voltage and the number of bits ($N$). In this model, resolution is the voltage step between adjacent ladder thresholds, or one LSB (least significant bit).
  $\Delta U = \frac{U_{REF}}{2^N}$
• Quantization error: This is the difference between the actual analog input voltage and the value assigned to the output code. With an ideal rounding quantizer, the error is at most $\pm \frac{1}{2}$ LSB.
• Conversion time: This is the time from application of the input signal until the digital output is valid. In a simplified model, it includes the delay of the slowest comparator together with the encoder and remaining output logic. The comparators operate in parallel, so the delay does not grow linearly with the number of bits, although higher resolution increases the number of circuit elements and their loading.

Transfer Characteristic and the R/2 Shift

The converter's transfer characteristic relates the analog input voltage to the digital output code. In the ideal model, it has a staircase shape.

In a simple ladder with equal resistors R, code transitions occur at integer multiples of the resolution step. Using R/2 resistors at the two ends of the ladder shifts the thresholds by half an LSB. This places the centers of the quantization intervals around the code values and, in the ideal model, reduces the mean quantization error.