A/D Converter Methods

From Analog to Digital

An Analog-to-Digital Converter (ADC) is an electronic circuit that converts a continuous analog signal, such as a microphone voltage, into a discrete digital representation, namely a binary number. This representation allows digital systems, including computers, to process, store, and transmit signals from the physical world.

ADC conversion methods can be divided into two main families according to how the transformation is carried out:

• Direct conversion methods: These methods compare the input voltage directly with a series of reference voltages to determine the digital output. They usually shorten conversion time but require more circuit elements.
• Indirect conversion methods: These methods first convert the analog voltage into an intermediate quantity, such as time or frequency, and then measure that quantity to produce the digital result. They usually operate more slowly but can provide high accuracy.

Direct Method 1: The Flash (Parallel) ADC

A Flash ADC is among the fastest ADC architectures. It performs comparisons between the input voltage and all threshold levels in parallel, hence the alternative name parallel ADC.

Operating principle

The architecture consists of three key parts:

1. Resistor ladder: A chain of $L_R = 2^N$ identical resistors creates a set of precise reference voltages. For an $N$-bit converter, this ladder provides $2^N-1$ internal comparison thresholds.
2. Comparator Bank: The core of the converter is a bank of $L_K = 2^N-1$ comparators. The unknown input voltage $V_{IN}$ is applied to one input of every comparator, while the other input of each comparator is connected to a unique tap on the resistor ladder.
3. Decoder: The comparator outputs form a "thermometer code": comparators with thresholds below the input return '1', while the others return '0'. A digital decoder converts this code into a standard $N$-bit binary output.

Direct Method 2: Successive Approximation ADC

The Successive Approximation Register (SAR) ADC is a widely used architecture that combines speed, resolution, and cost in one design. It uses a binary search to determine the code corresponding to the input voltage.

Operating principle

In the idealized approximation phase, an $N$-bit converter performs one comparison per bit, or $N$ clock cycles:

1. Initialize: The SAR sets the most significant bit (MSB) to '1' and all other bits to '0'.
2. Convert to analog: This test code is fed into a Digital-to-Analog Converter (DAC), which for a unipolar input range from 0 to $V_{REF}$ generates an analog voltage equal to half of the reference voltage ($V_{REF}/2$).
3. Compare: The comparator determines whether the input voltage $V_{IN}$ is higher or lower than the DAC output.
4. Decide and iterate: If $V_{IN}$ is higher than the DAC output, the MSB remains '1'. If it is lower, the MSB is cleared. The SAR then moves to the next bit, sets it to '1', and the DAC generates a new test level ($V_{REF}/2 \pm V_{REF}/4$), depending on the previous decision. The process covers all $N$ bits, from most to least significant, narrowing the possible value at each step.

Indirect Method: Dual-Slope Integrating ADC

Integrating ADCs provide high accuracy and reduce the effect of some interference, but they convert more slowly. In a dual-slope architecture, the measurement integrates the input voltage and then returns the integrator to its starting level with a reference voltage.

Operating principle

The conversion happens in two distinct phases:

1. Phase 1 (input integration): The unknown input voltage $V_{IN}$ is applied to an integrator for a fixed period, $T_1$. During this time, a counter counts a fixed number of clock pulses ($N_{max}$). The integrator output changes linearly, and its value after $T_1$ is proportional to the input voltage.
2. Phase 2 (reference de-integration): The integrator input is switched from $V_{IN}$ to a stable, known negative reference voltage, $-V_R$, where $V_R$ denotes the positive magnitude. The integrator output moves in the opposite direction and returns to zero. The counter is reset and counts clock pulses until a comparator detects zero. The return time, $T_2$, corresponds to the number of clock pulses, $N$, counted in this phase.

For a positive input voltage $V_{IN}$ and $V_R > 0$, the count $N$ is proportional to $V_{IN}$. Factors from the integrator resistor (R) and capacitor (C) occur in both phases and cancel in the ratio of the times, so their tolerances have less effect on the result. The relationship is: $N = N_{max} \cdot \frac{V_{IN}}{V_R}$.