Frame Synchronization

Clock recovery and bit synchronization

A receiver must know the bit interval before it samples a digital waveform. The clock signal provides that timing reference and defines the instants at which the receiver decides whether the signal represents 0 or 1. The transmitter and receiver may start with different phases, and oscillator error changes the sampling instants over time.

A receiver can extract timing from the incoming data stream through clock recovery, also called bit synchronization. The recovered clock tracks the transmitter timing closely enough for sampling. Phase drift moves the sampling instant toward a symbol boundary and increases bit errors. The receiver therefore monitors both transition timing and sampling margin. This margin limits the tolerated phase error.

Frame synchronization is a separate stage after bit timing has been recovered. The receiver searches for the defined frame-alignment signal, checks its position in subsequent frames, and can use CRC information to reject false alignments.

Method 1: Recovery from self-clocking codes

A line code with regular transitions gives the receiver timing information. Self-clocking line codes, such as RZ (Return-to-Zero) and Manchester, provide transitions that carry timing information. RZ returns to zero within a symbol, while Manchester has a mandatory mid-bit transition. Their spectra contain energy near the clock frequency ($f_{\text{clk}}$).

Narrow-band filtering

A narrow-band filter can isolate energy near the clock frequency. Its passband and bandwidth must account for the line rate, oscillator tolerance, and expected jitter.

The process works as follows:

1. The incoming RZ or Manchester signal passes through a selective filter, such as a quartz or ceramic resonator, tuned near the clock frequency $f_{\text{clk}}$.
2. The filter attenuates components outside its passband and leaves a dominant sinusoidal component near the clock frequency. A real filter has finite bandwidth, so residual data components remain.
3. A shaping circuit, such as a comparator or limiter, converts this component into a square-wave clock for sampling.

Method 2: Recovery from codes without embedded timing (for example, NRZ)

NRZ (Non-Return-to-Zero) does not guarantee a transition in every bit interval. A run of equal bits holds a constant level and supplies little timing information. Such a run can leave the loop without a new edge for several bit periods. The receiver forms timing pulses from transitions when they occur and tracks the oscillator between those pulses.

Edge detection and PLL

The recovery typically uses a Phase-Locked Loop (PLL) whose reference is formed from pulses generated at data edges.

1. An edge detector circuit watches the incoming NRZ signal. It's designed to produce a short timing pulse ($u_{\text{imp}}$) every time the signal changes its state (from low to high or high to low).
2. These intermittent pulses are fed into a PLL.
3. The PLL uses these pulses as a reference to adjust its internal oscillator. During a run of identical bits, the oscillator continues at its latest estimated frequency. A later edge allows the PLL to correct phase and frequency. The holdover interval depends on oscillator frequency error and loop design.
4. This process results in a stable, continuous clock signal even when the data itself has few transitions. The allowed run length and jitter determine the available phase-correction range.