Clock Recovery - Technical Implementation

Phase-locked loop (PLL) fundamentals

A receiver can recover timing with a . The loop adjusts an oscillator so its phase and frequency follow a reference derived from transitions in the incoming data. The oscillator output supplies the sampling clock and tracks the transmitter timing.

Phase Detector

Compares the reference and feedback phases

Loop Filter

Filters phase error and drives the VCO

Voltage-Controlled Oscillator

Generates the recovered clock

PLL architectures for clock recovery

1. Analog PLL

Analog PLLs process continuous-time signals throughout the loop. Noise and jitter depend on the phase detector, loop filter, oscillator, and circuit implementation.

Components: Analog phase detector, RC loop filter, LC VCO
Advantages: Low jitter in suitable designs, wide frequency range
Disadvantages: Process sensitivity, higher power consumption

2. Digital PLL (DPLL)

A DPLL represents phase comparison and loop filtering with digital logic, which enables programmable parameters and integration with digital systems.

Components: Digital phase detector, digital loop filter, DCO
Advantages: Programmability, integration with digital logic, reduced sensitivity to component variations
Disadvantages: Quantization noise, finite resolution limitations

3. All-Digital PLL (ADPLL)

An ADPLL performs phase detection, filtering, and oscillator control in the digital domain. It fits integrated designs that already contain digital timing logic.

Components: TDC, digital loop filter, digital-controlled oscillator
Advantages: Digital implementation, straightforward integration of test logic
Disadvantages: Requires high-speed digital circuits

Clock recovery from line codes

Self-clocking codes

Manchester includes a transition within each bit, while RZ returns to its reference level during a symbol. These transitions provide timing information.

f_{\text{clock}} = \frac{1}{T_{\text{bit}}}

Codes without embedded timing

NRZ and AMI do not guarantee a transition during each bit interval. The receiver must track the transitions that occur and hold the oscillator between them.

\Delta t = t_{\text{edge},n} - t_{\text{edge},n-1}

Performance metrics

Clock jitter

Jitter is variation of an edge or clock period relative to its ideal timing. Clock recovery circuits must keep this variation within the interface or system limit.

Types of jitter

Phase Jitter: Phase variation relative to ideal timing
Period Jitter: Variation in a clock period
Cycle-to-Cycle Jitter: Difference between adjacent clock periods

PLL transfer function

For a linearized unity-feedback model:

H(s) = \frac{K_d \cdot K_v \cdot F(s)}{s + K_d \cdot K_v \cdot F(s)}