The role of memory in network devices
Modern switches and routers use memory during packet and cell switching. Memory temporarily stores data units to handle contention, meaning that several streams compete for the same output link. This temporary storage is called buffering.
In this context, network memory can be divided into traditional electronic memory, such as RAM, and specialized concepts for optical memory developed for all-optical networks. At the circuit level, memory can use latches and flip-flops, while larger systems use components such as SRAM, DRAM, ROM, and flash.
Electronic memory in a modern router
A contemporary switching node, such as an IP router, uses several types of electronic memory. Each type serves a distinct function in the device.
- In a typical router architecture, it is the workspace for current data. It stores items such as the running configuration, routing tables, and packet buffers. When packets arrive faster than they can be transmitted, they are queued in RAM. Specific devices can also use fast SRAM or higher-capacity DRAM.
- Depending on the design, it stores the boot program or part of it. It contains instructions for starting the router and locating the main operating system, similar to a personal computer's BIOS. In some devices, the boot function is implemented in flash or in a separate ROM device.
- It stores the router's operating system and saved configuration files. Unlike RAM, Flash retains its data when power is removed. Erasing and programming are performed electrically, so the contents can be updated without replacing the device.
Buffering strategies in electronic switches
In ATM and high-speed packet switching, the way cells or packets are buffered affects performance. Buffering handles contention when several inputs want to send data to the same output at the same time. The buffer location and management method define the switch's architecture.
1. Input buffering and HOL blocking
In this model, each input port has its own buffer for incoming packets. An arbiter decides which input can transmit to an output in each time slot. This simple organization has an important limitation, . To reduce HOL, a switch can use virtual output queues (VOQ), in which each input port maintains a separate queue for each output port.
2. Output buffering
Packets pass through the switching fabric to a buffer at each output port. This architecture avoids HOL blocking. With equal port rates, up to packets can arrive for the same output at once, requiring up to writes and one read during the transmission time of a packet. In a simplified model, the incoming path must run at times the rate of one line, while the memory must also serve the read. This makes the architecture demanding and expensive in large switches.
3. Shared memory buffering
This architecture uses one central buffer shared by all input and output ports. Incoming packets are written to the memory, while a control unit manages pointers and creates logical queues for the output ports. Dynamic allocation improves the use of buffer space. With equal port rates and full load, up to writes and reads can be required in one interval, so the total memory bandwidth must be at least times the line rate.
The challenge and solution of optical buffering
All-optical packet switching keeps the signal in the optical domain and limits electronic conversions. It faces a buffering problem because propagating light cannot easily be stopped and stored. There is no widely available, inexpensive optical equivalent of electronic RAM.
One common solution is the . The packet is routed through a fiber section or loop with a selected length. It travels farther and reaches its destination later, providing temporary buffering.
Optical buffer architectures
- Traveling type buffers These use parallel FDLs with different lengths and delay times, such as . A packet requiring a certain delay is switched into the appropriate line.
- Recirculating type buffers These use a single fiber loop. A packet can circulate through the loop repeatedly to obtain a longer delay. Optical gates and switches control the number of passes.
In a typical design, only one packet can be written to or read from the buffer at a given moment. An FDL delays a signal but does not provide arbitrary access like RAM. WDM (Wavelength Division Multiplexing) can reduce this limitation by allowing one fiber loop to buffer several packets simultaneously on different wavelengths.