Flip-Flops | Teleinf Edu

A memory element in digital systems

A flip-flop is a digital circuit that stores a single bit, 0 or 1. A logic gate produces an output from its current inputs, while a flip-flop output depends on the inputs and the previous state. This property allows flip-flops to store state in memory and sequential-logic circuits.

Sequential and combinational logic

Flip-flop operation requires a distinction between two types of digital circuits:

Its output is determined solely by current input values. The circuit does not store information about earlier inputs. Examples include AND, OR, and NOT gates and adders.
Its output depends on current inputs and the previous input sequence represented by the current state. The circuit uses memory elements such as flip-flops to store that state.

A basic memory element: the SR latch

The simplest latch is the SR Latch (Set-Reset Latch), constructed from two cross-coupled NOR or NAND gates. It has two inputs, S (Set) and R (Reset), and two outputs, Q and its complement $\bar{Q}$ .

Operation of an SR latch (NOR version)

Set ( $S=1, R=0$ ) Q is forced to '1' and $\bar{Q}$ becomes '0'. The circuit stores the set state.
Reset ( $S=0, R=1$ ) Q is forced to '0' and $\bar{Q}$ becomes '1'. The circuit stores the reset state.
Hold and memory ( $S=0, R=0$ ) Q and $\bar{Q}$ retain their previous state. This is the information-storage mode.
Forbidden state ( $S=1, R=1$ ) This combination forces both Q and $\bar{Q}$ to '0', so they are no longer complements. If both inputs return to S=0, R=0 at the same time, the final state can be unpredictable. The combination is therefore not used during normal operation.

Synchronization: the D flip-flop

Predictable sampling in a digital circuit is provided by a control signal called a . The D (Data or Delay) flip-flop is widely used in modern electronics. In its data path, it forces opposite values at Set and Reset, removing the forbidden SR input combination.

The D flip-flop has one data input, D. An internal inverter supplies opposite values to the Set and Reset inputs of the underlying latch, eliminating the S=R=1 condition in the data path.

How it works

An D flip-flop samples its D input at the active clock edge, such as the rising edge. The sampled value appears at Q and remains there until the next active edge. The clock input therefore defines the sampling moment. The relationship is $Q_{\text{next}} = D$ .

JK and T flip-flops

The JK Flip-Flop

The JK flip-flop extends the SR flip-flop. It has inputs J, corresponding to set, and K, corresponding to reset. When J=1, K=1, it changes to the opposite state on the active clock edge, so the SR forbidden combination is not required.

$J=0, K=0$ Hold state, with no change.
$J=1, K=0$ Set state, $Q=1$ .
$J=0, K=1$ Reset state, $Q=0$ .
$J=1, K=1$ Toggle state, with output $Q$ changing to its opposite value.

The T flip-flop

The T (Toggle) flip-flop is a simplified JK flip-flop with its J and K inputs tied together. It has one input, T. When $T=1$ , the output toggles on each active clock edge. When $T=0$ , the output holds its state. It is used in binary counters and frequency dividers, because each T flip-flop in a chain divides the clock frequency by two.

Applications of flip-flops

Flip-flops store state in many digital systems. Common applications include:

Registers Groups of D flip-flops form registers that store multi-bit data words, such as a byte in an 8-bit register. Registers are used in CPU operations.
Static RAM (SRAM) The fast memory used for CPU caches is built from arrays of bistable cells based on cross-coupled inverters. Each cell stores one bit of cache data.
Counters Chains of T or JK flip-flops form digital counters that count events or clock pulses.
Frequency dividers A T flip-flop divides the frequency of its input clock signal by two, which is useful in timing circuits.