Counters

Introduction to digital counters

A digital counter stores a state representing the number of occurrences of an event or a stage in a sequence, and its outputs can expose that value. It is a basic digital-logic circuit used in computing systems for counting, complex sequence generation, and frequency measurement. In a binary design, successive values are encoded as combinations of bits, so overflow starts the next complete sequence. The maximum rate depends on the technology, propagation delays, and clocking method. A car odometer or a handheld tally counter provides a familiar comparison. A digital counter performs the same function through clocked state transitions.

Counters are built from a cascade of flip-flops, where each flip-flop can store one bit of information. An $N$-bit counter, constructed from $N$ flip-flops, can count from 0 up to $2^N - 1$.

Asynchronous (ripple) counters

In a typical binary asynchronous counter, also called a "ripple" counter, the flip-flops do not receive a common clock edge. A change at the output of one flip-flop triggers the clock input of the next one in the chain. The stages therefore change one after another, and the signal frequency is divided at each stage.

Operation and characteristics

• Simple design A typical circuit consists of flip-flops connected in series, without additional logic gates between successive stages.
• Propagation delay Each flip-flop is triggered by the previous one, so every stage adds a delay (propagation delay). For an $N$-bit counter, the settling time of the final bit is approximately the sum of the delays of the individual stages. This limits the maximum clock frequency at which the counter can operate reliably.
• Decoding glitches During a state transition, the outputs do not change at the same time. For a brief interval, the counter can present a transient value that is different from both stable states. This matters when the output controls another logic circuit.

Synchronous counters

A synchronous counter reduces the cascading delay and ripple-related glitches of an asynchronous counter. All flip-flops use a common clock signal and respond to the same edge. Common timing updates the successive bits within one clock cycle. Additional combinational logic determines whether a particular flip-flop changes state and computes the next state.

Operation and characteristics

• High speed All flip-flops receive the same clock edge. The settling time depends on the flip-flop delay and the delay through the control-logic path, so the counter can operate at a higher frequency than a ripple counter.
• Fewer ripple glitches A common clock edge limits transient values caused by ripple propagation. Delays in flip-flops and combinational logic can still produce short pulses in decoders.
• More complex design Additional logic gates control the state of individual flip-flops, making the circuit more complex, especially when the counter has many bits.

Counter configurations and special types

In addition to the asynchronous and synchronous categories, counters can include other features. The selected configuration depends on the required state sequence, operating speed, and control method:

• Up/down counters An additional control input determines whether the value increases or decreases with each clock pulse.
• Decade (BCD) counters These counters cycle through ten states, from 0 to 9, and then return to the start of the sequence. They are used for decimal displays that represent values in Binary-Coded Decimal (BCD). They have a modulo of 10.
• Ring countersThese counters use a shift register whose last flip-flop output feeds back to the first input. After proper initialization, a single '1' circulates around the "ring," which supports simple sequencing tasks.
• Johnson counters These resemble ring counters, but the inverted output of the last stage feeds back to the first. An $N$-bit Johnson counter produces $2N$ states, two states for each stage.